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Data Sheet
ADM1075
HOT SWAP FAULT RETRY
The ADM1075 turns off the FET after an overcurrent fault.
OV RISING = OV THRESHOLD ×
R TOP + R BOTTOM
R BOTTOM
With the default pin configuration, the part latches off after an
overcurrent fault and LATCH goes active low. This condition
can then be r eset by either a power cycling event or a low signal
to either the SHDN input or RESTART input. It can also be
reset by toggling the UVx pin, using the PMBus operation
command or the PMBus power cycle command.
If the LATCH pin is connected to the SHDN pin, the part
makes seven attempts to hot swap before latching off. In this
mode, the part uses the TIMER pin to time a delay between
each attempt. In this way, a large load capacitance can be
charged using consecutive current limit periods.
The part can also be configured to autoretry an infinite number of
times with a 10 second cooling period between each retry. Connect-
ing LATCH to RESTART means that the part makes one hot
swap attempt between each cooling period. Connecting LATCH
to SHDN and GPO2/ALERT2 to RESTART means that the part
makes seven hot swap attempts between each cooling period.
OV FALLING ≈ OV RISING / ( R TOP × 5 μA )
The UV detector is split into two separate pins, UVH and UVL.
The voltage on the UVH pin is compared internally to a 1 V
reference, whereas the UVL pin is compared to a 0.9 V reference.
Therefore, if the pins are tied together, the UV hysteresis is 100 mV.
The hysteresis can be adjusted by placing a resistor between
UVL and UVH.
connection. An external resistor network divides the supply
voltage for monitoring. An undervoltage event is detected when
the voltage connected to the UVL pin falls below 0.9 V, and the
gate is shut down using the 10 mA pull-down device. The fault
is cleared after UVH pin rises above 1.0 V.
Similarly, when an overvoltage event occurs and the voltage on
the OV pin exceeds 1 V, the gate is shut down using the 10 mA
pull-down device.
–48V RTN (0V)
The duty cycle of the automatic retry cycle is set by the ratio of
2 μA/60 μA, which approximates to being on ~4% of the time.
The value of the timer capacitor determines the on time of this
cycle, which is calculated as follows:
UVH
VIN
+
R SHUNT
C1
t ON = V TIMERH × ( C TIMER /60 μA)
t OFF = ( V TIMERH ? V TIMERL ) × ( C TIMER /2 μA)
A 470 nF capacitor on the TIMER pin gives ~8 ms of on time
(for example, to meet 10 ms SOA), and ~220 ms off time.
UVL
OV
1V
0.9V
1V
–
+
–
–
+
GATE
ENABLE
LOGIC
ADM1075
GATE
SENSE+
SENSE–
Q1
R SENSE
FAST RESPONSE TO SEVERE OVERCURRENT
The ADM1075 features a very fast detection circuit that quickly
responds to severe overcurrent events such as short circuits.
Such an event may cause catastrophic damage if not controlled
very quickly. A fast response circuit ensures that the ADM1075
detects an overcurrent event at approximately 150% of the normal
current limit (ISET) and responds and controls the current
within 1 μs in most cases. The severe overcurrent threshold
and glitch filter times are digitally programmable through the
PMBus. The threshold can be selected as 125%, 150%, 200%, or
225% of the normal current limit, and the glitch filter time can
be set to 200 ns, 900 ns, 10.7 μs, or 57 μs. This sets a maximum
response time of 300 ns, 950 ns, 13 μs, or 60 μs.
UV AND OV
The ADM1075 monitors the supply voltage for undervoltage
(UV) and overvoltage (OV) conditions. The OV pin is con-
nected to the input of an internal voltage comparator, and its
voltage level is internally compared with a 1 V voltage reference.
The user can program the value of the OV hysteresis by varying
the top resistor of the resistor divider on the pin. This impedance
VEE
–48V
Figure 52. Undervoltage and Overvoltage Supply Monitoring
The maximum rating on the UVH pin is 4 V and the UVH
threshold is 1 V. This limits the maximum input voltage to
minimum input voltage ratio to 4:1. For example, if the UVH
threshold is set at 20 V, the maximum input voltage is 80 V so
as not to exceed the maximum ratings of the pin. If a wider
input range is required, some protection circuitry is required
on the UV pins to limit them to less than 4 V.
PWRGD
The PWRGD output indicates the status of the output voltage.
As shown in Figure 53, the PWRGD output is derived from the
DRAIN pin voltage. It is an open-drain output that pulls low
when the voltage on DRAIN is less than 2 V and the GATE pin
voltage is near its 12 V rail (power good). When a fault occurs
or hot swap is turned off, the open-drain pull-down is disabled,
allowing PWRGD to go high (power bad). PWRGD is guaran-
teed to be in a valid state for V IN ≥ 1 V.
in combination with the 5 μA OV hysteresis current (current
turned on after OV trips) sets the OV hysteresis voltage.
Rev. C | Page 25 of 52
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